In integrated circuits, a device isolation layer electrically insulates neighboring semiconductor devices such as transistors. As the integrated circuits become more highly integrated, there is a desire to develop insulation technologies that can be used in a small area of an integrated circuit substrate.
Trench isolation has become widely used. A trench device isolation layer may be formed by etching a predetermined region of an integrated circuit substrate such as a semiconductor substrate to a pre-set depth to form a trench. Then, the trench is filled with an insulation layer. The trench device isolation layer can occupy a small area and can have superior insulation characteristics compared to an isolation layer that is formed by conventional local oxidation of silicon (LOCOS).
FIGS. 1 and 2 are cross-sectional views showing methods of forming a conventional trench device isolation layer.
Referring to FIG. 1, a buffer oxide layer 2 and a hard mask layer 3 are sequentially formed on a substrate 1. The hard mask layer 3 and the buffer oxide layer 2 are successively patterned to expose a predetermined region of the substrate 1. The exposed substrate 1 is selectively etched to form a trench 4 having a predetermined depth from top of the substrate 1. A sidewall oxide layer 5 is formed on sidewalls and a bottom (floor) of the trench 4. The buffer oxide layer 2 is formed of silicon oxide and the hard mask layer 3 is formed of silicon nitride. The sidewall oxide layer 5 is formed of thermal oxide.
A conformal liner layer 6 is formed on the surface of the substrate 1 and in the trench 4. A device insulation layer 7 is formed on the liner layer 6 to fill the trench 4. The liner layer 6 is formed of silicon nitride and the device insulation layer 7 is formed of silicon oxide.
Referring now to FIG. 2, the device insulation layer 7 is planarized until the liner layer 6 is exposed, to form a device isolation layer 7a in the trench 4. The exposed liner layer 6 and the hard mask layer 3 are etched by a wet etch process, thereby forming a liner 6a in the trench 4. In this case, a dent 8 may occur at top of sidewalls of the device isolation layer 7a. That is to say, while the liner 6a is formed, edges of the liner 6a are etched by the wet etch process, such that the dent 8 may occur.
The buffer oxide layer 2 is removed to expose the substrate 1 and a gate oxide layer 9 and a gate electrode 10, which are sequentially stacked, are formed on the substrate 1. As shown in FIG. 2, the gate electrode 10 may be formed in the dent 8. Therefore, characteristics of transistors that include the gate electrode 10 can be degraded. For example, a hump or inverse narrow width effect may occur in the transistors.